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SerDes & PHY

  • 1 to 12.5 Gb/s SerDes PHY, multi-standard for FPGA, 28 nm CMOS process
  • 4 Channel 3.125 Gb/s SerDes PHY, 10GBase-KX4 / XAUI, 45 nm CMOS process.
  • 10 Gb/s SerDes CDR, 10GBase-KR / XFI, 65 nm CMOS process.
  • 1 to 6 Gb/s SerDes CDR, multi-standard for FPGA, 65 nm CMOS process.
  • 1 to 6 Gb/s SerDes CDR, multi-standard for FPGA, in 90 nm CMOS process.
  • 1.5, 3 Gb/s SerDes PHY, SAS / SATA PHY, 0.13/0.11 um CMOS process.
  • 2.5 Gb/s SerDes PHY, PCIE, 0.13 um CMOS process.
  • 1.5 Gb/s SerDes PHY, SATA, 0.18/0.11 um CMOS process.
  • 1 Gb/s DLL based clock/data aligner PHY, SPI-4 & HyperTransport, 0.11um CMOS process.

PLL & DLL

  • Low phase noise, 2.5 GHz base band PLL for Wireless Apps, 65 nm CMOS process.
  • Low phase noise, 1.5 GHz base band PLL & clock multiplier for Wireless Application, 90 nm CMOS process.
  • Low phase noise, 1056 MHz base band PLL & clock multiplier for Wireless Application, 0.13 um CMOS process.
  • 700 MHz, multi-output clock generating PLL with fractional feed-back ratio, 0.13 um CMOS process.
  • 150 MHz digital PLL with high ratio (~5000) clock multiplier using direct digital period synthesis (DDPS) technique, 0.11 um CMOS process.
  • 266 MHz DLL for DDR application, 0.13 um CMOS process.

 

 

Please contact us for detailed technical information, customization, and support services.

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